Mimcap structure in a semiconductor device package

ABSTRACT

The disclosed technology relates generally to a semiconductor device package comprising a metal-insulator-metal capacitor (MIMCAP). In one aspect, the MIMCAP is formed between a first and second metallization layers in a stack of metallization layers, e.g., copper metallization layers formed by single damascene processes. The MIMCAP comprises a bottom plate formed in the first metallization layer, a first conductive layer on and in electrical contact with the bottom plate, a dielectric layer on and in contact with the first conductive layer, a second conductive layer on and in contact with the dielectric layer, and a top plate formed in the second metallization layer, on and in electrical contact with the second metal plate. The electrical contacts to the bottom and top plates of the MIMCAP formed in the first and second metallization layer are thereby established without forming separate vias between the plates and the metallization layers. In addition, the first conductive layer of the MIMCAP may extend beyond the surface of the dielectric and the second layer for forming other structures.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application claims foreign priority to European patent applicationEP 12194922.6 filed on Nov. 29, 2012, the content of which isincorporated by reference herein in its entirety.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The disclosed technology relates generally to semiconductor processing,and more particularly to integration of a metal-insulator-metalcapacitor in the back-end-of-line (BEOL) processing of a semiconductorpackage.

2. Description of the Related Technology

Device downscaling in present day CMOS technology is leading to fasterswitching speeds of the transistors integrated with a higher density onthe semiconductor wafer. However, in the final device, large currentspikes may occur due to a large number of ‘simultaneous’ switchingevents in the circuit within a short period of time, which can causeconsiderable current-resistance drop and noise over the power supplynetwork. Voltage fluctuation and power supply noise may impact signalintegrity, speed and reliability of the devices. It has been shown thatthe addition of an on-chip decoupling MIMCAP (Metal-Insulator-Metalcapacitor) can reduce this problem and enhance circuit performance. TheMIMCAP can compensate voltage fluctuations by delivering charges to thepower-supply network. However, its capacitance needs to be large enoughto be actually efficient. In addition, low resistance and low inductanceis needed to enable the efficient application of MIMCAPs at highfrequencies. In present day MIMCAP designs, resistance especially is toohigh for this purpose because of the connections from at least one ofthe metallization layers to the top and/or the bottom plate of theMIMCAP. Such connections are established by via etching and fillingtechniques, typically increasing the resistance of the path from themetallization layer(s) to the MIMCAP.

SUMMARY OF CERTAIN INVENTIVE ASPECTS

The disclosed technology is related to a MIMCAP design that does notsuffer from the above-described problem. The technology is particularlyrelated to a MIMCAP structure as disclosed in the appended claims and toa method for producing such a structure. A MIMCAP according to anembodiment is formed between first and second metallization layers in astack of metallization layers, e.g., copper metallization layers, formedby damascene processes. The stack can support one or more semiconductordevices, which are connected through the metallization layers to anexternal power source. The MIMCAP comprises a bottom plate in the firstmetallization layer, a first conductive layer on and in electricalcontact with the bottom plate, a dielectric layer on and in contact withthe first conductive layer, a second conductive layer on and in contactwith the dielectric layer, and a top plate in the second metallizationlayer, on and in electrical contact with the second metal plate. Thecontacting of the bottom and top plates of the MIMCAP from the first andsecond metallization layer is thereby established without vias betweenthe plates and the metallization layers. In addition, the firstconductive layer of the MIMCAP may extend beyond the surface of thedielectric and the second layer for forming other structures.

In one aspect, a semiconductor device package comprises one or moresemiconductor devices electrically coupled to a metallization stackcomprising a plurality of interconnected metallization layers. Thesemiconductor device package additionally includes ametal-insulator-metal capacitor formed between a lower layer (M1) of themetallization layers and an upper layer (M2) of the metallizationlayers, where the lower and upper layers are adjacent metallizationlayers within the stack. The capacitor includes at least a portion of abottom plate which forms a part of the lower metallization layer (M1).The capacitor additionally includes at least a portion of a firstconductive layer on and in contact with the bottom plate, a dielectriclayer on and in contact with the first conductive layer, and a secondconductive layer on and in contact with the dielectric layer. Thecapacitor further includes a top plate which forms a part of the uppermetallization layer, the top plate being on and in contact with thesecond conductive layer.

According to an embodiment, the first and second conductive layer andthe dielectric layer in between the layers have the same size in theplane of the layers.

According to another embodiment, the first conductive layer extendsbeyond the surface of the dielectric layer and the second dielectriclayer.

In the latter case, the first conductive layer may be patterned in thearea outside the area covered by the MIMCAP. The first conductive layermay be patterned to form one or more patterned portions, which serve ascontact portions for electrical circuit elements in the lower or uppermetallization layer and/or which serve themselves as the electricalcircuit elements.

According to an embodiment, a patterned portion of the first conductivelayer forms a resistor in the upper metallization layer, and wherein astack of a dielectric layer portion and a top conductive layer portionis present on top of the resistor, the dielectric layer and topconductive layer portion being of the same material and thickness of thedielectric layer and second conductive layer of the capacitor.

According to an embodiment, the second conductive layer is surrounded inthe plane of the layer by a ring structure of the same material andthickness of the second conductive layer.

The first and second metallization layer may be the power supply layerand the ground layer respectively of an interposer substrate carryingone or more integrated circuit devices.

The bottom and/or top plate may be provided with perforations throughthe complete thickness of the plates, the perforations being filled witha dielectric material.

The invention is equally related to a method for producing asemiconductor package according to the invention, comprising theprocesses of:

-   -   Producing a first metallization layer by a damascene process,        the first metallization layer comprising a bottom plate,    -   Depositing a stack of a first conductive layer, a dielectric        layer and a second conductive layer on and in contact with the        first metallization layer,    -   Patterning at least the second layer and the dielectric layer to        form a stack of the first conductive layer or a portion thereof,        the dielectric layer and the second conductive layer, which        covers at least partially the bottom plate,    -   Producing a second metallization layer by a damascene process,        the second metallization layer comprising a top plate which is        on and in contact with the second conductive layer of the stack.

In the method of the invention, the patterning step may be performed tothe effect of forming a stack of the first conductive layer, thedielectric layer and the second conductive layer, the layers being ofthe same size in the plane of the layers.

According to another embodiment, the patterning step is performed to theeffect of forming a stack of the dielectric layer and the secondconductive layer on top of the first conductive layer, the firstconductive layer remaining intact after the patterning step.

According to an embodiment, the first conductive layer is furtherpatterned in a second patterning step. During the second patterningstep, the first conductive layer and the second conductive layer portionof the stack may be patterned simultaneously.

During the second patterning step, the second conductive layer portionof the stack may be patterned to form a ring structure around a centralportion of the second conductive layer.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1 a to 1 g illustrate a method of fabricating a MIMCAP structureaccording to one embodiment.

FIGS. 2 a to 2 e illustrate a method of fabricating a MIMCAP structureaccording to another embodiment.

FIGS. 3 a to 3 c illustrate a method of fabricating a MIMCAP accordingto another embodiment.

FIGS. 4 a and 4 b illustrate a device structure according to oneembodiment.

FIGS. 5 a and 5 b illustrate a resistor device that can be fabricatedtogether with a MIMCAP according to one embodiment.

DETAILED DESCRIPTION OF CERTAIN ILLUSTRATIVE EMBODIMENTS

As used herein, a metallization layer refers to a layer or a stack oflayers including a dielectric material and a pattern of electricallyconductive material embedded in the layer or the stack of layersincluding the dielectric material. Subsequent metallization layers inthe stack are isolated from each other except through verticalconnections between the electrically conductive material.

As used herein, a patterning process refers to a fabrication process inwhich portions of a layer are removed by etching away the portions whilethe remainder of the layer is protected by an etch mask, leaving apattern formed by the remaining parts of the layer. The patterning maytake place by known photolithography techniques involving a resistlayer, or by hard mask techniques, equally known in the art.

FIGS. 1 a-1 g illustrate a method of fabricating a MIMCAP according toone embodiment. In the illustrated embodiment, the MIMCAP is formedbetween two copper metallization layers produced on a substrate. Thesubstrate may for example be an active or passive interposer substrateonto which various integrated circuit chips are to be assembled. FIG. 1a shows a base substrate 1, provided with an isolation layer 2 over thesubstrate. In some embodiments, the base substrate 1 comprises siliconand the isolation layer 2 comprises a layer formed of, for example,silicon oxide, silicon nitride, silicon carbide or a combination (e.g. astack) of two or three of these materials. Alternatively, in otherembodiments, the substrate may comprise a glass substrate (i.e. insteadof the combined Si+isolation layer).

On the substrate 1, a first metallization layer M1 is provided, whichcan be formed, for example, by a damascene process as known in the art.A first layer 3 of inter-metal dielectric (IMD) is deposited, andpatterned by a patterning step as defined above, to form openings and/ortrenches, which can then be lined with a barrier layer for preventingCu-diffusion into the IMD combined with a copper seed deposited by asuitable deposition technique (such as physical or chemical vapourdeposition—PVD or CVD), as known in the art. After that, copper isplated (using electrochemical deposition ECD) to fill openings and/ortrenches. The copper which has been plated not only in the openings andtrenches but also on top of the IMD, is planarized by a CMP (ChemicalMechanical Polishing) process, which leads to the result shown in FIG. 1b. The barrier layer is not shown in this drawing for clarity. In thedisclosed method, the first metallization layer M1 thus obtainedcomprises at least one plate 4 which is to form the bottom plate of theMIMCAP. This may be a rectangular plate for example. The bottom plate 4is preferably provided with perforations (not shown) filled withdielectric, which serve to maintain flatness of the bottom plate duringCMP. The perforations are obtained as non-etched IMD portions during theIMD patterning step, onto which the copper is deposited, the copperfilling the spaces between the IMD portions.

By way of an example, three additional copper structures 5 are shown,which can include, for example, conductors running along a pre-definedpattern in the first metallization layer M1. Then a stack of threelayers (6, 7, 8) is deposited on the planarized surface (FIG. 1 c), forexample by PVD deposition processes, including a first electricallyconductive layer 6, a dielectric layer 7 and a second electricallyconductive layer 8. In the rest of this description and in the claims,these electrically conductive layers 6 and 8 will be referred to as‘conductive layers’ for reasons of conciseness. The conductive layersmay be formed of metal layers or layers of conductive materials, e.g,TiN or TaN. The stack of layers 6/7/8 is then patterned, to form aMIM-stack 9 (FIG. 1 d), which covers at least a portion of the bottomplate 4. This is followed by the deposition of a further IMD layer 10(FIG. 1 e), which is patterned to form at least one opening 11 on top ofthe MIM-stack, as well as vias 12 towards some of the structures 5 (FIG.1 f). By another damascene process, the openings are filled with copperand planarized, resulting in the second metallization layer M2,comprising the top plate 13 (which can be perforated as described abovefor the first metallization layer M1, for maintaining flatness), incontact with the second conductive layer 8 of the MIM-stack (FIG. 1 g),as well as via connections 14 for connecting the structures 5 with afurther metallization layer. The final MIMCAP-structure 50 comprises aportion of the bottom plate 4, the first conductive layer 6, thedielectric layer 7, the second conductive layer 8 and the top plate 13.

In embodiments of the method described herein, no via connections areformed towards the top or bottom plate of the MIMCAP. According toembodiments, the MIMCAP includes the bottom plate 4, the firstconductive layer 6 in contact with the bottom plate 4, the dielectriclayer 7 in contact with the first conductive layer 6, the secondconductive layer 8 in contact with the dielectric layer 7, and the topplate 13 in contact with the second conductive layer, wherein the bottomplate is part of a first metallization layer and the top plate is partof a second metallization layer in a metallization stack coupled betweenone or more semiconductor devices and an external power source.

According one embodiment, the formation of the MIM-stack 9 takes placeby multiple patterning processes, wherein in the first patterning step,the first conductive layer 6 remains intact on the surface of theplanarized first metallization layer M1, while the dielectric 7 and thesecond conductive layer 8 are patterned to form a stack of these twolayers covering at least a portion of the bottom plate 4. After that, asecond patterning step is performed to pattern the first conductivelayer 6 and possibly the second conductive layer 8 simultaneously. Inthis way, the first conductive layer can be used to form additionalstructures within the first metallization layer M1.

This embodiment is illustrated in FIGS. 2 a-2 e. FIG. 2 a shows thestage where the stack of layers 6/7/8 described in relation to FIG. 1,has been deposited on the planarized first metallization layer M1. Thestructures 15 comprise a part of an inductor pattern in the firstmetallization layer M1, while the MIM-stack also extends over a portion3′ of the IMD 3 of M1, with no metal present in the portion. FIG. 2 bshows the result of a first patterning step wherein only the dielectriclayer 7 and the second conductive layer 8 are patterned to form aMIM-stack 9 which covers at least a portion of the bottom plate 4. TheMIM-stack 9 comprises the remainder of the dielectric layer 7, thesecond conductive layer 8 and a portion of the first conductive layer 6,where the first conductive layer 6 remains intact on the surface of thefirst metallization layer M1. That is, etching of layers 7 and 8 stopson the first conductive layer 6, for example, by choosing an etchanthaving a suitable selectivity between etch rates of the first conductivelayer 6 and the dielectric layer 7.

In a second patterning step, the first conductive layer 6 is patterned,as shown in FIG. 2 c. Portions 20 and 21 of the layer 6 to the left andright of the MIM stack remain. Furthermore, a portion 22 above theinductor structure 15 and covering the entire inductor structure remainsas well. Finally, a rectangular portion 23 remains on the portion 10′ ofthe IMD. These portions 20 to 23 of the first conductive layer 6 can nowserve as additional structural elements in the metallization layout.Deposition and patterning of the second metallization layer M2 resultsin the view of FIG. 2 d, once again with the top copper plate 24 on andin contact with the second conductive layer 8 of the MIM-stack. A via 25is produced for contacting the first conductive layer 6 and thus thebottom plate 4 from the second metallization layer M2. Vias 26 areprovided for contacting the inductor 15, while rectangular vias 27, asseen in the top view of FIG. 2 e, are produced for connecting therectangular portion 23 of the first conductive layer to the secondmetallization layer M2. In this way, the rectangular portion 23 may beintegrated as a resistor in the circuit defined within the secondmetallization layer M2.

The function of the inductor shaped portion 22 of layer 6 and of theportion 21 to the right of the MIMCAP (contacted by via 25) is toprovide a possible advantage in the processing of the M1 and M2 layers.When etching the vias 25 and 26 for example, the etching stops on thefirst conductive layer 6 (e.g. a TaN layer), and not on the Cu. Stoppingon a Cu layer can lead to contamination of the etching chamber, whichcomplicates the process. The presence of the first conductive layer 6makes it possible to avoid those complications (by patterning theportion 22) at least during processing of the M1 and M2 layers, which isparticularly advantageous given the high copper density of the layers M1and M2. So even though the invention is not limited (as seen in FIG. 1for example) to the embodiment wherein portions of the first conductivelayer 6 remain on inductors and/or other structures in the M1 layer, theinvention does represent a considerable advantage in providing thispossibility.

In some embodiments, the patterned portion 22 of layer 6 can also serveas at least a part of an inductor (i.e. without the inductor pattern 15in the M1 layer). In some embodiments, the patterned layer 22 can serveas a stand-alone inductor without the inductor pattern 14, incircumstances where the thickness of the inductor pattern 22 issufficient for serving as a workable inductor. In general, the patternedportions of the first conductive layer 6 may serve as contact portionsfor structures (such as inductor 15) in one of the metallization layersM1/M2 or the portions may themselves play the part of circuit elementsin the metallization layers (such as the resistor 23, or theoretically,the inductor pattern 22).

In a still further embodiment, the patterning process for patterning thefirst conductive layer 6 serves also to pattern portions of the secondconductive layer 8 that forms the top layer of the MIM stack 9.According to an embodiment illustrated in FIGS. 3 a-3 c, this patterningis to the effect that a ring structure 30 (not necessarilycircular-shaped) is formed surrounding a central portion 31 of the topconductive layer 8, in the plane of the MIMCAP. The top copper plate 24then only contacts the central portion 31. The ring portion 30 serves toprevent possible shorting between the top and bottom electrodes at theedge of the capacitor. The structure of the MIMCAP of the invention, andits fabrication method allows formation of such a protective ring 30simultaneously with the patterning of the first conductive layer 6, andthus provides an economic way of producing complex structures.

According to another embodiment, the first conductive layer 6 remainsintact after a first patterning process, as in the embodiments of FIGS.2 and 3, however, unlike in the embodiments of FIGS. 2 and 3, but in thesecond patterning process, it is only the second conductive layer 8which is further patterned, for example to form a ring structure 30,while the first conductive layer 6 still remains intact. Examplestructures fabricated by this embodiment is illustrated in FIGS. 4 a and4 b. In these embodiments, there is no separate process of processing aseparate bottom plate having dimensions that are in the same order ofmagnitude as the top plate 13 or 24. The bottom plate of the MIMCAP is aportion of a larger metal layer in the M1-layer.

According to an embodiment, the process of patterning the dielectriclayer 7 and the second conductive layer 8 of the MIM-stack, with thefirst conductive layer 6 remaining intact, does not only take place atthe location of the eventual MIMCAP above the bottom plate 4, butsimilar stacks of portions 7′ and 8′ formed by patterning the layers 7and 8 may also remain on other locations. In embodiments illustrated inFIGS. 5 a and 5 b, additional stacks 40 including the portions 7′ and 8′are produced on the resistor portion 23. In some embodiments, the stacks40 protect a large portion of the resistor metal during the etching ofthe dielectric 7 in other areas. This therefore allows a better controlof the resistance value of the resistor. The stack 40 may be furtherprovided with a connection 28 to the next metallization layer (FIG. 5b).

In some embodiments, the IMD material may be formed of silicon oxide(SiO₂), a combination of SiO₂ with silicon nitride (Si₃N₄) or acombination of SiO₂ and silicon carbide (SiC). In other embodiments, theIMD may be formed of a low-k material. In some embodiments, the metalmaterial of the metallization comprises copper. In some embodiments, theM1 and M2 layers may have thicknesses according to known practice in thedomain of damascene processing, e.g. around 1 micron. In someembodiments, the thickness of the M2 layer may be chosen higher than M1given that the CMP process will generally take longer as the topographycaused by the MIM-stack patterning needs to be removed.

In some embodiments, the first and second conductive layer 6/8 of theMIM-stack may be formed of, for example, Ta, TaN, Ti, TiN, or othersuitable conductive materials. The layers 6, 7 and 8 preferably have thesame thickness, e.g. between about 50 nm and about 100 nm. At least thethickness of the first and second conductive layer 6 and 8 is preferablythe same, especially in the embodiment of FIG. 2, where both layers areetched in the same etching process.

In some embodiments, the dielectric layer 7 of the MIM-stack may beformed of, for example, silicon oxide (e.g., SiO₂), silicon nitride(e.g., Si₃N₄), silicon carbide (e.g., SiC), tantalum oxide (e.g.,Ta₂O₅), hafnium oxide (e.g., HfO₂), titanium oxide (e.g., TiO₂), anONO-stack (Oxide-nitride-oxide), or any other suitable dielectricmaterial.

According to an embodiment, an annealing process can be performed priorto performing a CMP process on the first metallization layer M1. In oneembodiment, the annealing temperature is between about 350° C. and about450° C. The annealing is done to decrease hillocks formation due tostress induced by the subsequent processes (MIM-stack deposition).

The embodiments disclosed herein can be integrated with existing BEOLprocess schemes. According to an embodiment, for example, variousembodiments of the MIMCAP structures described above can be integratedwith an interposer substrate, in particular between the power supplylayer the ground layer of such an interposer. This is particularlyadvantageous due to the large surface that is available for the MIMCAP.

While the invention has been illustrated and described in detail in thedrawings and foregoing description, such illustration and descriptionare to be considered illustrative or exemplary and not restrictive.Other variations to the disclosed embodiments can be understood andeffected by those skilled in the art in practicing the claimedinvention, from a study of the drawings, the disclosure and the appendedclaims. In the claims, the word “comprising” does not exclude otherelements or processes, and the indefinite article “a” or “an” does notexclude a plurality. The mere fact that certain measures are recited inmutually different dependent claims does not indicate that a combinationof these measures cannot be used to advantage. Any reference signs inthe claims should not be construed as limiting the scope.

The foregoing description details certain embodiments of the invention.It will be appreciated, however, that no matter how detailed theforegoing appears in text, the invention may be practiced in many ways,and is therefore not limited to the embodiments disclosed. It should benoted that the use of particular terminology when describing certainfeatures or aspects of the invention should not be taken to imply thatthe terminology is being re-defined herein to be restricted to includeany specific characteristics of the features or aspects of the inventionwith which that terminology is associated.

Unless specifically specified, the description of a layer being formed,deposited or produced ‘on’ another layer or substrate, includes:

-   -   the layer being formed, deposited or produced, or formed,        deposited or deposited directly on, i.e. in contact with, the        other layer/layers and/or the substrate, and    -   the layer being formed, deposited or produced on one or a stack        of intermediate layers between the layer and the other layer        and/or the substrate.

What is claimed is:
 1. A semiconductor device package comprising: one ormore semiconductor devices electrically coupled to a metallization stackcomprising a plurality of interconnected metallization layers; and ametal-insulator-metal capacitor (MIMCAP) formed between a lower layer ofthe metallization layers and an upper layer of the metallization layers,the lower and upper layers being adjacent metallization layers withinthe stack, wherein the MIMCAP comprises: at least a portion of a bottomplate which forms a part of the lower metallization layer, at least aportion of a first conductive layer on and in contact with the bottomplate, a dielectric layer on and in contact with the first conductivelayer, a second conductive layer on and in contact with the dielectriclayer, and a top plate which forms a part of the upper metallizationlayer, the top plate being on and in contact with the second conductivelayer.
 2. The semiconductor package of claim 1, wherein the first andsecond conductive layers and the dielectric layer interposed between thefirst and second conductive layers have substantially the same coveragearea and overlap one another when viewed in a direction perpendicular toa lateral plane of the layers.
 3. The semiconductor package of claim 1,wherein the first conductive layer laterally extends beyond the areas ofcoverage covered by the dielectric layer and the second conductivelayer.
 4. The semiconductor package of claim 3, wherein the firstconductive layer is further patterned in an area outside of an areacovered by the MIMCAP.
 5. The semiconductor package of claim 4, whereinthe first conductive layer is patterned to form one or more patternedportions, wherein the patterned portions serve as contact portions forelectrical circuit elements.
 6. The semiconductor package of claim 3,wherein the first conductive layer is patterned to form one or morepatterned portions, wherein the patterned portions serve as electricalcircuit elements formed in at least one of the lower or uppermetallization layers.
 7. The semiconductor package of claim 6, wherein apatterned portion of the first conductive layer forms a resistor in theupper metallization layer, and wherein a stack including a dielectriclayer portion and a top conductive layer portion is formed on theresistor, wherein the dielectric layer portion is formed of the samematerial and has the same thickness as the dielectric layer of theMIMCAP, and wherein the top conductive layer portion is formed of thesame material and has the same thickness as the second conductive layerof the MIMCAP.
 8. The semiconductor package of claim 3, wherein thesecond conductive layer is surrounded in a plane of the secondconductive layer by a ring structure formed of the same material andhaving the same thickness as the second conductive layer.
 9. Thesemiconductor package of claim 1, wherein the lower and uppermetallization layers form a power supply layer and a ground layer,respectively, of an interposer substrate carrying the one or moreintegrated circuit devices.
 10. The semiconductor package of claim 1,wherein at least one of the bottom plate and the top plate is providedwith perforations formed therethrough, wherein the perforations are atleast partially filled with a dielectric material.
 11. A method offabricating a semiconductor package, comprising: forming a firstmetallization layer by a damascene process, the first metallizationlayer comprising a bottom plate; depositing a stack comprising a firstconductive layer in contact with the first metallization layer, adielectric layer and a second conductive layer; patterning the stack toremove at least portions of the second conductive layer and thedielectric layer, wherein the stack at least partially covers the bottomplate; and forming a second metallization layer by a damascene process,the second metallization layer comprising a top plate which is on and incontact with the second conductive layer of the stack.
 12. The method ofclaim 11, wherein patterning the stack comprises forming the stackhaving each of the first conductive layer, the dielectric layer and thesecond conductive layer covering substantially the same coverage areaand overlapping one another when viewed in a direction perpendicular toa lateral plane of the layers.
 13. The method of claim 11, whereinpatterning the stack forms a stack including the dielectric layer andthe second conductive layer on the first conductive layer, wherein thefirst conductive layer remains intact after patterning the stack. 14.The method of claim 13, wherein the first conductive layer is furtherpatterned in a second patterning process.
 15. The method of claim 14,wherein during the second patterning process, the first conductive layerand the second conductive layer of the stack are patternedsimultaneously.
 16. The method of claim 14, wherein during the secondpatterning process, the second conductive layer of the stack ispatterned to form a ring structure around a central portion of thesecond conductive layer.